FIG. 1 shows a schematic diagram of a conventional synchronous switching mode voltage regulator 10, which comprises an output stage 12 connected between an input voltage Vin and ground GND to generate an output voltage Vout, and a pulse width modulator (PWM) 14 responsive to the output voltage Vout to generate a PWM signal P1 by which the output stage 12 is driven. The output stage 12 includes a high-side switch 122 connected between the input voltage Vin and a phase node 124, and a low-side switch 126 connected between the phase node 124 and ground GND. The pulse width modulator 14 has an error amplifier 142 to generate an error signal SEA by comparing the output voltage Vout with a reference voltage VREF, and a PWM comparator 144 connected with the error signal SEA and a ramp signal SRAMP to generate a PWM signal P1, by which the high-side switch 122 and low-side switch 126 are turned on/off. When the output voltage Vout is decreased, the ON duty of the PWM signal P1 is increased so as to increase the ON time of the high-side switch 122, and thereby raising the output voltage Vout to the desired value. The circuit 10 has advantages of high efficiency and rapid response at high and moderate loadings. However, the efficiency of the circuit 10 may be decreased due to the power consumption caused by the fact that the inductor current IL flowing toward the low-side switch 126 as a result of the decreased frequency and the reduced ON duty at light loading, for example at idle mode.
Efficiency is important for the PWM regulator, particularly for portable apparatus applications. However, the efficiency of a typical switching mode regulator may be decreased as its loading is reduced, this is due to the fact that a constant amount of the power is wasted in the switching drive circuit thereof, being independent of the magnitude of the loading thereon. For the improvement of the efficiency, a switching mode voltage regulator disclosed by U.S. Pat. No. 6,307,356 issued to Dwelley employs a fixed minimum non-zero duty cycle generator to generate a signal at the idle mode with an ON duty wider than that of the PWM signal for switching the high-side switch, so as to avoid the current flowing toward the low-side switch from the inductor and thereby without the reduction in the efficiency of the regulator circuit. However, according to the second law of voltage balanceΔIL=(Vin−Vout)×TON/L=Vout×TOFF/L,where ΔIL is the variation of the inductor current IL, TON is the ON time of the high-side switch, TOFF is the OFF time of the high-side switch, and L is the inductance of the inductor. The variation ΔIL of the inductor current IL will be decreased if the difference (Vin−Vout) is decreased while the ON time TON remains unchanged. Furthermore, the OFF time TOFF will be decreased with the almost unchanged output voltage Vout, and then the number of the switching in the switching circuit will be increased, thereby causing the increased switching loss, and the decreased efficiency will be effected. Such a problem also occurs in an asynchronous switching mode voltage regulator.
Therefore, it is desired improved efficiency for a switching mode voltage regulator and method thereof.